// Copyright (C) 1991-2013 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions 
// and other software and tools, and its AMPP partner logic 
// functions, and any output files from any of the foregoing 
// (including device programming or simulation files), and any 
// associated documentation or information are expressly subject 
// to the terms and conditions of the Altera Program License 
// Subscription Agreement, Altera MegaCore Function License 
// Agreement, or other applicable license agreement, including, 
// without limitation, that your use is for the sole purpose of 
// programming logic devices manufactured by Altera and sold by 
// Altera or its authorized distributors.  Please refer to the 
// applicable agreement for further details.

// *****************************************************************************
// This file contains a Verilog test bench with test vectors .The test vectors  
// are exported from a vector file in the Quartus Waveform Editor and apply to  
// the top level entity of the current Quartus project .The user can use this   
// testbench to simulate his design using a third-party simulation tool .       
// *****************************************************************************
// Generated on "07/31/2016 01:04:24"
                                                                        
// Verilog Self-Checking Test Bench (with test vectors) for design :    mult1
// 
// Simulation tool : 3rd Party
// 

`timescale 1 ps/ 1 ps
module mult1_vlg_sample_tst(
	A,
	B,
	clk,
	Enter,
	Mostrar,
	Mult,
	resetn,
	sampler_tx
);
input [7:0] A;
input [3:0] B;
input  clk;
input  Enter;
input  Mostrar;
input  Mult;
input  resetn;
output sampler_tx;

reg sample;
time current_time;
always @(A or B or clk or Enter or Mostrar or Mult or resetn)
                                                                                
begin                                                 
 if ($realtime > 0)                                   
 begin                                                
	if ($realtime == 0 || $realtime != current_time)  
	begin									          
		if (sample === 1'bx)                          
			sample = 0;                               
		else                                          
			sample = ~sample;                         
	end										          
	current_time = $realtime;					      
 end                                                  
end                                                   

assign sampler_tx = sample;
endmodule

module mult1_vlg_check_tst (
	A_in_,
	B_in,
	B_in_0,
	en_ACUM,
	en_R1,
	en_R2,
	Fin,
	ld_R1,
	ld_R2,
	P,
	Sel,
	Sel_muestra,
	Termine,
	sampler_rx
);
input [7:0] A_in_;
input [3:0] B_in;
input  B_in_0;
input  en_ACUM;
input  en_R1;
input  en_R2;
input  Fin;
input  ld_R1;
input  ld_R2;
input [7:0] P;
input  Sel;
input  Sel_muestra;
input  Termine;
input sampler_rx;

reg [7:0] A_in__expected;
reg [3:0] B_in_expected;
reg  B_in_0_expected;
reg  en_ACUM_expected;
reg  en_R1_expected;
reg  en_R2_expected;
reg  Fin_expected;
reg  ld_R1_expected;
reg  ld_R2_expected;
reg [7:0] P_expected;
reg  Sel_expected;
reg  Sel_muestra_expected;
reg  Termine_expected;

reg [7:0] A_in__prev;
reg [3:0] B_in_prev;
reg  B_in_0_prev;
reg  en_ACUM_prev;
reg  en_R1_prev;
reg  en_R2_prev;
reg  Fin_prev;
reg  ld_R1_prev;
reg  ld_R2_prev;
reg [7:0] P_prev;
reg  Sel_prev;
reg  Sel_muestra_prev;
reg  Termine_prev;

reg  Fin_expected_prev;
reg [7:0] P_expected_prev;
reg  Termine_expected_prev;

reg  last_Fin_exp;
reg [7:0] last_P_exp;
reg  last_Termine_exp;

reg trigger;

integer i;
integer nummismatches;

reg [1:13] on_first_change ;


initial
begin
trigger = 0;
i = 0;
nummismatches = 0;
on_first_change = 13'b1;
end

// update real /o prevs

always @(trigger)
begin
	A_in__prev = A_in_;
	B_in_prev = B_in;
	B_in_0_prev = B_in_0;
	en_ACUM_prev = en_ACUM;
	en_R1_prev = en_R1;
	en_R2_prev = en_R2;
	Fin_prev = Fin;
	ld_R1_prev = ld_R1;
	ld_R2_prev = ld_R2;
	P_prev = P;
	Sel_prev = Sel;
	Sel_muestra_prev = Sel_muestra;
	Termine_prev = Termine;
end

// update expected /o prevs

always @(trigger)
begin
	Fin_expected_prev = Fin_expected;
	P_expected_prev = P_expected;
	Termine_expected_prev = Termine_expected;
end



// expected Fin
initial
begin
	Fin_expected = 1'bX;
end 

// expected Termine
initial
begin
	Termine_expected = 1'bX;
end 
// expected P[ 7 ]
initial
begin
	P_expected[7] = 1'bX;
end 
// expected P[ 6 ]
initial
begin
	P_expected[6] = 1'bX;
end 
// expected P[ 5 ]
initial
begin
	P_expected[5] = 1'bX;
end 
// expected P[ 4 ]
initial
begin
	P_expected[4] = 1'bX;
end 
// expected P[ 3 ]
initial
begin
	P_expected[3] = 1'bX;
end 
// expected P[ 2 ]
initial
begin
	P_expected[2] = 1'bX;
end 
// expected P[ 1 ]
initial
begin
	P_expected[1] = 1'bX;
end 
// expected P[ 0 ]
initial
begin
	P_expected[0] = 1'bX;
end 
// generate trigger
always @(A_in__expected or A_in_ or B_in_expected or B_in or B_in_0_expected or B_in_0 or en_ACUM_expected or en_ACUM or en_R1_expected or en_R1 or en_R2_expected or en_R2 or Fin_expected or Fin or ld_R1_expected or ld_R1 or ld_R2_expected or ld_R2 or P_expected or P or Sel_expected or Sel or Sel_muestra_expected or Sel_muestra or Termine_expected or Termine)
begin
	trigger <= ~trigger;
end

always @(posedge sampler_rx or negedge sampler_rx)
begin
`ifdef debug_tbench
	$display("Scanning pattern %d @time = %t",i,$realtime );
	i = i + 1;
	$display("| expected A_in_ = %b | expected B_in = %b | expected B_in_0 = %b | expected en_ACUM = %b | expected en_R1 = %b | expected en_R2 = %b | expected Fin = %b | expected ld_R1 = %b | expected ld_R2 = %b | expected P = %b | expected Sel = %b | expected Sel_muestra = %b | expected Termine = %b | ",A_in__expected_prev,B_in_expected_prev,B_in_0_expected_prev,en_ACUM_expected_prev,en_R1_expected_prev,en_R2_expected_prev,Fin_expected_prev,ld_R1_expected_prev,ld_R2_expected_prev,P_expected_prev,Sel_expected_prev,Sel_muestra_expected_prev,Termine_expected_prev);
	$display("| real A_in_ = %b | real B_in = %b | real B_in_0 = %b | real en_ACUM = %b | real en_R1 = %b | real en_R2 = %b | real Fin = %b | real ld_R1 = %b | real ld_R2 = %b | real P = %b | real Sel = %b | real Sel_muestra = %b | real Termine = %b | ",A_in__prev,B_in_prev,B_in_0_prev,en_ACUM_prev,en_R1_prev,en_R2_prev,Fin_prev,ld_R1_prev,ld_R2_prev,P_prev,Sel_prev,Sel_muestra_prev,Termine_prev);
`endif
	if (
		( Fin_expected_prev !== 1'bx ) && ( Fin_prev !== Fin_expected_prev )
		&& ((Fin_expected_prev !== last_Fin_exp) ||
			on_first_change[7])
	)
	begin
		$display ("ERROR! Vector Mismatch for output port Fin :: @time = %t",  $realtime);
		$display ("     Expected value = %b", Fin_expected_prev);
		$display ("     Real value = %b", Fin_prev);
		nummismatches = nummismatches + 1;
		on_first_change[7] = 1'b0;
		last_Fin_exp = Fin_expected_prev;
	end
	if (
		( P_expected_prev[0] !== 1'bx ) && ( P_prev[0] !== P_expected_prev[0] )
		&& ((P_expected_prev[0] !== last_P_exp[0]) ||
			on_first_change[10])
	)
	begin
		$display ("ERROR! Vector Mismatch for output port P[0] :: @time = %t",  $realtime);
		$display ("     Expected value = %b", P_expected_prev);
		$display ("     Real value = %b", P_prev);
		nummismatches = nummismatches + 1;
		on_first_change[10] = 1'b0;
		last_P_exp[0] = P_expected_prev[0];
	end
	if (
		( P_expected_prev[1] !== 1'bx ) && ( P_prev[1] !== P_expected_prev[1] )
		&& ((P_expected_prev[1] !== last_P_exp[1]) ||
			on_first_change[10])
	)
	begin
		$display ("ERROR! Vector Mismatch for output port P[1] :: @time = %t",  $realtime);
		$display ("     Expected value = %b", P_expected_prev);
		$display ("     Real value = %b", P_prev);
		nummismatches = nummismatches + 1;
		on_first_change[10] = 1'b0;
		last_P_exp[1] = P_expected_prev[1];
	end
	if (
		( P_expected_prev[2] !== 1'bx ) && ( P_prev[2] !== P_expected_prev[2] )
		&& ((P_expected_prev[2] !== last_P_exp[2]) ||
			on_first_change[10])
	)
	begin
		$display ("ERROR! Vector Mismatch for output port P[2] :: @time = %t",  $realtime);
		$display ("     Expected value = %b", P_expected_prev);
		$display ("     Real value = %b", P_prev);
		nummismatches = nummismatches + 1;
		on_first_change[10] = 1'b0;
		last_P_exp[2] = P_expected_prev[2];
	end
	if (
		( P_expected_prev[3] !== 1'bx ) && ( P_prev[3] !== P_expected_prev[3] )
		&& ((P_expected_prev[3] !== last_P_exp[3]) ||
			on_first_change[10])
	)
	begin
		$display ("ERROR! Vector Mismatch for output port P[3] :: @time = %t",  $realtime);
		$display ("     Expected value = %b", P_expected_prev);
		$display ("     Real value = %b", P_prev);
		nummismatches = nummismatches + 1;
		on_first_change[10] = 1'b0;
		last_P_exp[3] = P_expected_prev[3];
	end
	if (
		( P_expected_prev[4] !== 1'bx ) && ( P_prev[4] !== P_expected_prev[4] )
		&& ((P_expected_prev[4] !== last_P_exp[4]) ||
			on_first_change[10])
	)
	begin
		$display ("ERROR! Vector Mismatch for output port P[4] :: @time = %t",  $realtime);
		$display ("     Expected value = %b", P_expected_prev);
		$display ("     Real value = %b", P_prev);
		nummismatches = nummismatches + 1;
		on_first_change[10] = 1'b0;
		last_P_exp[4] = P_expected_prev[4];
	end
	if (
		( P_expected_prev[5] !== 1'bx ) && ( P_prev[5] !== P_expected_prev[5] )
		&& ((P_expected_prev[5] !== last_P_exp[5]) ||
			on_first_change[10])
	)
	begin
		$display ("ERROR! Vector Mismatch for output port P[5] :: @time = %t",  $realtime);
		$display ("     Expected value = %b", P_expected_prev);
		$display ("     Real value = %b", P_prev);
		nummismatches = nummismatches + 1;
		on_first_change[10] = 1'b0;
		last_P_exp[5] = P_expected_prev[5];
	end
	if (
		( P_expected_prev[6] !== 1'bx ) && ( P_prev[6] !== P_expected_prev[6] )
		&& ((P_expected_prev[6] !== last_P_exp[6]) ||
			on_first_change[10])
	)
	begin
		$display ("ERROR! Vector Mismatch for output port P[6] :: @time = %t",  $realtime);
		$display ("     Expected value = %b", P_expected_prev);
		$display ("     Real value = %b", P_prev);
		nummismatches = nummismatches + 1;
		on_first_change[10] = 1'b0;
		last_P_exp[6] = P_expected_prev[6];
	end
	if (
		( P_expected_prev[7] !== 1'bx ) && ( P_prev[7] !== P_expected_prev[7] )
		&& ((P_expected_prev[7] !== last_P_exp[7]) ||
			on_first_change[10])
	)
	begin
		$display ("ERROR! Vector Mismatch for output port P[7] :: @time = %t",  $realtime);
		$display ("     Expected value = %b", P_expected_prev);
		$display ("     Real value = %b", P_prev);
		nummismatches = nummismatches + 1;
		on_first_change[10] = 1'b0;
		last_P_exp[7] = P_expected_prev[7];
	end
	if (
		( Termine_expected_prev !== 1'bx ) && ( Termine_prev !== Termine_expected_prev )
		&& ((Termine_expected_prev !== last_Termine_exp) ||
			on_first_change[13])
	)
	begin
		$display ("ERROR! Vector Mismatch for output port Termine :: @time = %t",  $realtime);
		$display ("     Expected value = %b", Termine_expected_prev);
		$display ("     Real value = %b", Termine_prev);
		nummismatches = nummismatches + 1;
		on_first_change[13] = 1'b0;
		last_Termine_exp = Termine_expected_prev;
	end

	trigger <= ~trigger;
end
initial 

begin 
$timeformat(-12,3," ps",6);
#1000000;
if (nummismatches > 0)
	$display ("%d mismatched vectors : Simulation failed !",nummismatches);
else
	$display ("Simulation passed !");
$finish;
end 
endmodule

module mult1_vlg_vec_tst();
// constants                                           
// general purpose registers
reg [7:0] A;
reg [3:0] B;
reg clk;
reg Enter;
reg Mostrar;
reg Mult;
reg resetn;
// wires                                               
wire [7:0] A_in_;
wire [3:0] B_in;
wire B_in_0;
wire en_ACUM;
wire en_R1;
wire en_R2;
wire Fin;
wire ld_R1;
wire ld_R2;
wire [7:0] P;
wire Sel;
wire Sel_muestra;
wire Termine;

wire sampler;                             

// assign statements (if any)                          
mult1 i1 (
// port map - connection between master ports and signals/registers   
	.A(A),
	.A_in_(A_in_),
	.B(B),
	.B_in(B_in),
	.B_in_0(B_in_0),
	.clk(clk),
	.en_ACUM(en_ACUM),
	.en_R1(en_R1),
	.en_R2(en_R2),
	.Enter(Enter),
	.Fin(Fin),
	.ld_R1(ld_R1),
	.ld_R2(ld_R2),
	.Mostrar(Mostrar),
	.Mult(Mult),
	.P(P),
	.resetn(resetn),
	.Sel(Sel),
	.Sel_muestra(Sel_muestra),
	.Termine(Termine)
);

// resetn
initial
begin
	resetn = 1'b0;
	resetn = #30000 1'b1;
end 

// clk
always
begin
	clk = 1'b0;
	clk = #10000 1'b1;
	#10000;
end 
// A[ 7 ]
initial
begin
	A[7] = 1'b0;
end 
// A[ 6 ]
initial
begin
	A[6] = 1'b0;
end 
// A[ 5 ]
initial
begin
	A[5] = 1'b0;
end 
// A[ 4 ]
initial
begin
	A[4] = 1'b0;
end 
// A[ 3 ]
initial
begin
	A[3] = 1'b0;
	A[3] = #30000 1'b1;
	A[3] = #120000 1'b0;
end 
// A[ 2 ]
initial
begin
	A[2] = 1'b0;
end 
// A[ 1 ]
initial
begin
	A[1] = 1'b0;
	A[1] = #30000 1'b1;
	A[1] = #120000 1'b0;
end 
// A[ 0 ]
initial
begin
	A[0] = 1'b0;
end 
// B[ 3 ]
initial
begin
	B[3] = 1'b0;
	B[3] = #170000 1'b1;
	B[3] = #80000 1'b0;
end 
// B[ 2 ]
initial
begin
	B[2] = 1'b0;
end 
// B[ 1 ]
initial
begin
	B[1] = 1'b0;
	B[1] = #170000 1'b1;
	B[1] = #80000 1'b0;
end 
// B[ 0 ]
initial
begin
	B[0] = 1'b0;
	B[0] = #170000 1'b1;
	B[0] = #80000 1'b0;
end 

// Enter
initial
begin
	Enter = 1'b0;
	Enter = #60000 1'b1;
	Enter = #70000 1'b0;
	Enter = #60000 1'b1;
	Enter = #50000 1'b0;
end 

// Mult
initial
begin
	Mult = 1'b0;
	Mult = #280000 1'b1;
	Mult = #60000 1'b0;
end 

// Mostrar
initial
begin
	Mostrar = 1'b0;
	Mostrar = #600000 1'b1;
	Mostrar = #60000 1'b0;
	Mostrar = #170000 1'b1;
	Mostrar = #50000 1'b0;
end 

mult1_vlg_sample_tst tb_sample (
	.A(A),
	.B(B),
	.clk(clk),
	.Enter(Enter),
	.Mostrar(Mostrar),
	.Mult(Mult),
	.resetn(resetn),
	.sampler_tx(sampler)
);

mult1_vlg_check_tst tb_out(
	.A_in_(A_in_),
	.B_in(B_in),
	.B_in_0(B_in_0),
	.en_ACUM(en_ACUM),
	.en_R1(en_R1),
	.en_R2(en_R2),
	.Fin(Fin),
	.ld_R1(ld_R1),
	.ld_R2(ld_R2),
	.P(P),
	.Sel(Sel),
	.Sel_muestra(Sel_muestra),
	.Termine(Termine),
	.sampler_rx(sampler)
);
endmodule